1. The PCIe 5.0 connector is a core component of the 5th-generation high-speed serial computer expansion bus standard. It is specifically designed to meet the requirements of a 32 GT/s transmission rate (with a one-way bandwidth of 4 GB/s per lane) and a total bandwidth of 128 GB/s (for x16 lanes), and is widely used in high-performance computing (HPC), data centers, and consumer electronics

2. Gold finger optimization: Gold fingers with a width of 0.6mm and a length of 3mm are adopted

3. Full-core shielding plane: A dense ground via array (with 1mm spacing) is used to suppress crosstalk and ensure high-frequency signal stability

4. Compatibility and expandability - Backward compatibility: Supports PCIe 4.0/3.0 devices

5. Protocol flexibility: Some products support multi-protocol functionality, adapting to hybrid storage and computing scenarios.

◆◆ Product Advantage

1. The single-lane speed reaches 32GT/s (with a bidirectional total bandwidth of approximately 63GB/s). It adopts 128b/130b encoding for efficient data transmission, which can meet the stringent requirements of the PCIe 5.0 specification for 36dB insertion loss (IL) and -10dB return loss (RL).

2. Impedance consistency design: It uses 85Ω differential impedance matching, and reduces reflections through complete ground planes in the inner layers of the PCB and metal shielding layers.

3. Equalization and pre-emphasis: The transmitter uses pre-emphasis to enhance high-frequency components, while the receiver adopts multi-level equalization (CTLE/DFE) to compensate for losses.

4. Crosstalk suppression: The gold finger area uses inner-layer GND planes to isolate Rx/Tx channels, and ground vias are evenly distributed between pins, significantly reducing near-end crosstalk (NEXT).

5. It complies with the PCI-SIG CEM 5.0 specification, adopts a 1.0mm pin pitch and SMT (Surface Mount Technology) process to ensure mechanical stability and soldering reliability. The metal housing and EMI springs provide electromagnetic shielding to reduce external interference.

6. It features full generational backward compatibility, with a physical interface completely consistent with that of PCIe 4.0/3.0 and support for automatic speed negotiation. For example, a PCIe 3.0 device can operate normally at 5GT/s when inserted into a Gen5 slot.

◆◆ Product Uses

1. AI Training Cluster

2. Storage Array

3. Desktop Computer/Laptop Computer

4. Edge Computing and Industrial Control

5. Communications and Network Equipment

◆◆ Product Documentation