Views: 0 Author: Site Editor Publish Time: 2026-08-29 Origin: Site
A training cluster going into service this year does not resemble the hardware most integration teams cut their teeth on. A single accelerator node weighs more than 60 kilograms, draws more power than an entire rack did ten years ago, and pushes board level links into territory that used to belong to the network layer.
Teams feel the consequences at the worst possible moment, usually during bring up, when a link that verified perfectly on the bench refuses to train at full width once the node is fully populated. Almost every one of those failures lands on a small part. Bandwidth roadmaps and accelerator allocations get the executive attention, while the pieces joining boards to cables get treated as catalog items.
AI server interconnect succeeds when you treat every mated interface as a budgeted resource. Allocate insertion loss the way you allocate watts, derate current for the inlet temperature and airflow your chassis actually has, set mating cycle targets from your real service model, and qualify the part against the assembly process that will build it. Get those four allocations right and the node comes up at full width. Miss one of them and the symptom surfaces as an intermittent link, a brownout under sustained load, or a field return that no firmware update will ever explain.
The rest of this article walks through that allocation work in the order we apply it on live programs. Every number comes from design review ranges rather than datasheet headlines, because headline figures describe a loose plug on a bench while your node runs at 45 C inlet, fully populated.
Table of Contents
AI hardware moves the goalposts on three axes at once: lane rate, current density, and service frequency. General purpose servers were designed around a modest number of 25 Gb/s to 56 Gb/s lanes, a few hundred watts, and a service model where a faulty box is swapped and shipped back. An AI node runs 112 Gb/s per lane today with 224 Gb/s on the roadmap, pulls 6 kW to 12 kW through the power entry, and gets opened repeatedly by technicians swapping accelerators or rerouting fabric cables. Designing to the older envelope is the most common root cause we find when a first generation platform cannot reach stable training throughput.
At 112 Gb/s PAM4 the Nyquist frequency sits near 28 GHz. Each mated interface contributes roughly 1.0 dB to 2.5 dB of insertion loss there, plus a return loss discontinuity that appears as a resonance between 20 GHz and 35 GHz. Two extra mated pairs cost more margin than 500 mm of extra low loss cable does, so we count interfaces rather than inches. A 1.0 mm press fit stub was harmless at 8 GT/s and becomes a measurable notch at 112 Gb/s.
Eight accelerators at 700 W to 1200 W each put a 4U node between 8 kW and 12 kW. That cannot arrive through the blade interfaces that fed a 500 W server, so power moves to busbars, laminated blades, or large format cable assemblies with contacts carrying 9 A to 20 A each. At those currents, resistance drift stops being academic: one contact moving from 5 milliohms to 12 milliohms dissipates over 2.7 W at 15 A.
A general purpose server is an appliance; when it fails, you replace it. An AI node is a capital asset rebuilt around whatever accelerators you can actually buy, so its interfaces must survive two or three accelerator generations plus repeated service. Interconnect is 2% to 5% of a node bill of materials, yet in our own return data it appears in roughly 18% to 30% of first year field failures traced back to the connection.
You choose interconnect for an accelerator dense node by writing down four allocations before you open any catalog: total insertion loss budget split across PCB, connector, and cable; maximum continuous current per contact after thermal derating; required mating cycles with an end of life resistance limit; and the assembly process the board will actually see. Parts that clear all four narrow to three or four families, and the decision between them turns on routing geometry and supply risk more often than raw electrical performance.
Every AI server connector decision we make starts with margin rather than headline speed. Ask the silicon vendor for the channel operating margin target and work backwards: a realistic 112 Gb/s allocation with one mated pair and 300 mm of twinax runs 6 dB to 8 dB in package and breakout, 1.5 dB to 2.0 dB for the mated interface, and 3 dB to 5 dB for the cable. Budget at least 0.3 dB of slop per interface, because supplier models come from clean evaluation boards, not your stack up. When the numbers do not close, use a shorter breakout, one fewer interface, or flyover cable.
Catalog values describe a loose plug in still air and run 30% to 40% above what a populated chassis supports. A contact rated 12 A as a loose plug carries roughly 7 A to 8 A in a populated shelf with 45 C inlet air and the airflow the fans can deliver at acoustic limits. Ask for the derating curve measured on the mated pair in representative airflow.
Condition | Contact rated 12 A | Contact rated 20 A | Busbar blade rated 60 A |
|---|---|---|---|
Loose plug reference | 12.0 A | 20.0 A | 60.0 A |
Populated chassis, 45 C inlet | 7.5 A to 8.5 A | 13.0 A to 14.5 A | 42.0 A to 46.0 A |
Populated chassis, 55 C inlet | 6.0 A to 7.0 A | 10.5 A to 12.0 A | 34.0 A to 38.0 A |
Service life belongs in the specification as well. Four service events a year over five years plus commissioning already put you past 25 cycles, so specify well beyond that, and specify the failure definition rather than only a cycle count: a maximum contact resistance shift of no more than 10 milliohms, plus a minimum retention force so the latch has not worn into something that backs out under fan vibration.
Match the interface to reach and routing rather than to habit. Board to board runs of 150 mm to 400 mm belong on the PCB with a high density mezzanine. Runs crossing the chassis, roughly 300 mm to 1000 mm, belong on twinax flyover cable. Anything leaving the rack belongs on optics. The electrical differences between candidate families matter less than whether you put copper where it has to bend and glass where it has to be cheap.
There is a real tendency in AI platform design to abandon everything that looks legacy, and for the socketed card interface that is usually a mistake. A PCIe connector still earns its place when you need a field replaceable slot with a mature compliance program, a wide ecosystem of expansion cards, and a mechanical envelope every technician understands. The argument is operational: you can swap an adapter without touching the fabric cable plant, and your support organization stocks one spare type instead of four.
The MCIO connector family exists because a cable based internal fabric removes routing pain that no layer count solves. Once you move 16 or 32 differential pairs across a chassis at 112 Gb/s, the board area needed to do it in trace becomes its own cost problem. Twinax buys you three things instead: predictable loss per unit length, airflow, because a bundle routes around a cold plate in ways a rigid board cannot, and serviceability, because a fabric cable can be replaced without pulling the main board.
Path type | Practical reach at 112 Gb/s | Best application | What it costs you |
|---|---|---|---|
PCB trace | up to about 250 mm | Same board, mezzanine, short riser | Layer count, stack up control, warpage |
Twinax flyover | 300 mm to 1000 mm | Chassis crossing, accelerator to switch tray | Assembly qualification, routing labor |
Copper to rack top | up to 3 m | Short reach cluster fabric | Power per bit, cable bulk in the hot aisle |
Optical | 10 m and beyond | Rack to rack, spine layer | Module cost, spares, cleaning discipline |
The crossover between trace and flyover arrives earlier than intuition suggests. Once breakout loss plus trace loss exceeds roughly 60% of the channel budget, cable is cheaper even before you count the layers you save.
Power interfaces in an AI node are thermal components first and electrical components second. Cold plates remove heat from the accelerator die and sometimes from memory, but the power entry region still sits in 45 C to 60 C air with limited airflow, and a contact running 30 C above ambient inside that space is a contact that will creep, oxidize, and drift. Specify by derated current at your worst case inlet temperature, never by the number printed for a loose plug.
Liquid cooling does not cool your interconnect, and this is the most expensive misconception in current platform design. A cold plate on the accelerators does almost nothing for the power entry or the harness feeding it, because those parts sit in whatever air is left, and in a densely packed node that air is warmer and slower than the air your team qualified against last decade. Measure rather than assume: on more than one program the contact barrel came back 15 C to 20 C above the thermal model because the harness crossed the top of a memory bank.
At 12 V a 10 kW node needs more than 830 A, which is why the industry runs 48 V to 54 V with local step down; even then you are moving 185 A into one node. Three families cover the need: busbars and laminated blades for high current and low cycle counts, large format cable assemblies for flexible routing, and board mount terminals for the final step down.
Interface family | Current per contact, new | Derated at 45 C inlet | Typical mating cycles |
|---|---|---|---|
Laminated busbar blade | 40 A to 120 A | 60% to 70% of rating | 25 to 50 |
Large format power contact | 9 A to 20 A | 65% to 75% of rating | 100 to 250 |
Board mount power terminal | 12 A to 25 A | 55% to 70% of rating | 25 to 100 |
High current cable lug | 100 A and above | 70% to 80% of rating | 10 to 25 |
None of these carry their nominal rating at realistic inlet temperatures, so build the derating into the contact count from the start. A power connector sized on bench numbers looks fine through bring up and then produces brownouts only during long training runs, which is the worst moment to discover an undersized power path.
Field reliability is decided by contact normal force and plating thickness, and both are invisible in a datasheet that lists only a mating cycle count. Ask for the resistance distribution after thermal cycling, ask for the normal force decay curve, and ask what thickness sits under the gold flash in the contact area. A part that survives 250 cycles on clean laboratory samples can fail in 60 cycles in a rack that sees dust, humidity swings, and a technician pulling on the cable instead of the latch.
Most commodity interconnect ships with gold flash over nickel, meaning 0.05 micron to 0.10 micron of gold. That is adequate for a handful of cycles in a clean environment and inadequate for an interface opened twenty times over five years by people whose gloves have touched a dusty floor. We specify a minimum of 0.38 micron of hard gold in the contact area for serviceable interfaces and require the measurement location in writing. The cost delta runs 15% to 30%, which is still small next to one depot return. On silver plated contacts the risk is different: silver tarnishes and the sulfide layer raises resistance, so specify mixed flowing gas exposure rather than salt spray alone.
Contact normal force sits in a narrow window. Too low, and vibration or thermal cycling produces fretting and intermittent resistance. Too high, and a 400 position part becomes impossible to mate by hand, which yields half seated connectors and bent contacts, the worst failure class because both are intermittent. We target 40 cN to 100 cN per signal contact with at least 0.8 mm of wipe so the contact cleans itself on insertion. Above roughly 120 N of total insertion force you need a lever, and above 250 N you need a redesign.
Require a test package built on production parts from three separate lots, not on golden samples. The minimum set is S parameters measured on your own footprint, a current derating curve at your inlet temperature, a durability run to at least 250 cycles with resistance recorded at intervals, mixed flowing gas exposure, thermal shock, and a reflow simulation on your actual stack up. If a supplier offers only pass fail statements without distributions, that is itself a qualification result.
Test | Condition | Sample size | Acceptance criteria |
|---|---|---|---|
High frequency characterization | S parameters to 40 GHz, your footprint | 5 parts, 3 lots | Within 0.3 dB of the model |
Current derating | Mated pair, 45 C and 55 C inlet | 10 parts | Rise below 30 C at derated current |
Mating durability | 250 cycles, resistance every 25 | 30 contacts | Delta below 10 milliohm, latch intact |
Mixed flowing gas | Relevant industry method, 500 hours | 15 contacts | Shift below 20% of initial |
Thermal shock | 500 cycles, 0 C to 100 C | 20 contacts | No cracking, no plating delamination |
Reflow simulation | Three profiles, your stack up | 3 boards | Coplanarity within 0.10 mm |
The details are negotiable; the structure is not. What you are buying is statistics. One passing sample tells you the part can work, while thirty samples with a distribution tell you it will work and give you a baseline if a future lot behaves differently.
Check two things before you believe a high frequency report. Confirm the fixture de embedding method and the reference plane, since a model referenced to a point inside the connector body flatters the part and the error compounds when models are cascaded in a channel simulation. Then confirm whether the data includes the mating transition, because several published loss figures exclude it, and that is the part which varies with wear.
Plan for two accelerator generations inside one chassis and qualify a second source on the day you release the first. Tooling lead time for a complex high speed part runs 10 to 16 weeks, plating capacity is the real bottleneck rather than molding, and gold content means pricing moves with the metal market. A program that starts after layout freeze costs you a quarter of schedule and leaves you single sourced anyway.
The chassis you are designing now will outlive the accelerators you can buy today. Reserve 20% to 30% more power contact capacity than the current generation draws, keep the fabric cable exit clear of the area where a taller next generation cold plate will sit, and avoid placing serviceable interfaces under anything that requires draining coolant to reach. Those constraints cost almost nothing at architecture time.
Pinout compatibility is not second sourcing. Two parts can be electrically interchangeable and still unusable as alternates if mating dimensions differ by a fraction of a millimeter, if panel cutouts do not match, or if termination tooling differs. Real readiness means four things: identical mating interface dimensions verified against a common envelope drawing, identical cutout and keepout, identical or documented alternative termination tooling, and cross mated qualification data.
Gold is a meaningful fraction of a high pin count part, and it is volatile, so ask for a metal pass through clause with a defined index, and ask which plating thickness the quote assumes. A quote that looks 12% cheaper is sometimes just a quote built on 0.05 micron instead of 0.38 micron, which you discover only when cycle testing fails. Plan 10 to 16 weeks for tooling and hold 8 to 12 weeks of safety stock on anything single sourced.
The decisions below determine whether an AI platform reaches stable throughput in the field. None are exotic, but they get deferred while the visible parts of the program consume the schedule, and they are expensive to revisit later.
Decision | Common default | What we recommend |
|---|---|---|
Loss allocation | Assigned after layout | Before placement, 0.3 dB slop per interface |
Current rating | Catalog value | Derated curve at worst case inlet |
Mating cycles | Minimum available | Two times the five year service estimate |
Plating | Gold flash | 0.38 micron minimum on serviceable contacts |
Qualification samples | Golden samples | Three lots, with distributions |
Second source | Deferred | Qualified at first release |
Safety stock | Set by finance | 8 to 12 weeks on single sourced parts |
Take the framing rather than any single number. Interconnect is not a component you select at the end of a design; it is a set of budgets you allocate at the beginning, and writing those budgets down is what separates platforms that scale from platforms that spend a year chasing intermittent faults.
What is the most common cause of link instability in AI server builds?
In our experience it is an unbudgeted mated interface rather than a defective part. A channel that simulated with adequate margin gains an extra connector during mechanical design for assembly convenience, and the loss shows up only when the node is fully populated. The fix is procedural: freeze the interface count as a specification item.
How many mating cycles should I specify for an AI node?
Take your realistic service estimate and double it. Four service events per year over five years plus commissioning put you near 25 cycles of intent, so specify a part qualified to 250 with a defined end of life resistance limit. The cycle count alone means nothing without that limit, since a part can survive 250 insertions and still drift out of specification.
Is copper still viable at 112 Gb/s per lane inside the rack?
Copper remains right inside the chassis and for short reach rack fabric, generally to about 3 m depending on cable gauge and retimer budget. Beyond that, power per bit and cable bulk limit you rather than signal integrity. The boundary is economic: weigh harness cost and blocked airflow against module cost plus the spares and cleaning discipline optics require.
Why does a power contact run hotter than the thermal model predicts?
Because the model assumes airflow that the harness itself blocks. Bundles routed across memory banks create stagnant regions where the contact barrel runs 15 C to 20 C above prediction. Instrument the contact and the jacket at the exit point, hold maximum load for four hours, and use that measurement instead of the model.
What should I require from a supplier before board layout freeze?
Three deliverables: a high frequency model generated on your stack up rather than a reference board, a derating curve measured on the mated pair at your inlet temperature and airflow, and coplanarity data after reflow on a board with your layer count. Missing any of the three means your layout rests on assumptions validated only after the tooling is cut, which is also why the decision belongs at architecture, before placement.
